JEDEC standard multilayer board 2S2P (2 signal, 2 power). If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Functional operation above the Recommended Operating Conditions is not implied. Stresses exceeding Maximum Ratings may damage the device. Symbol VDD VI TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input Voltage (VIN) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm (Note TSSOP16 TSSOP-16 Condition 1 GND 0 V GND 0 V GND VI v VDD Condition 2 Rating 36 265 Units V ☌ ☌/W ☌ For additional information, see Application Note AND8003/D. Moisture Sensitivity, Indefinite Time Out of Dray Pack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1.
Do not connectĬrystal Frequency Load Capacitance Shunt Capacitance, C0 Equivalent Series Resistance Initial Accuracy 25 ☌ Temperature Stability Aging C0/C1 RationĬharacteristic ESD Protection Human Body Model Value 2 kV Level in 7623 W) is connected to set the output current. These pins provide GND return path for the devices. Output enable input that tri-states output.
Connect a 25 MHz crystal or leave unconnected for clock input. Connect to 25 MHz crystal source or single-ended clock. Positive supply voltage pins are connected +3.3 V supply voltage. Pin Symbol Sel0 Sel1 VDD X2 OE GND IREF CLK NC I/O Input Power Supply Input Power Supply Output HCSL Output HCSL Output Description LVTTL/LVCMOS frequency select input 0. X1/CLK 25 MHz Clock or Crystal Clock Buffer Crystal Oscillator X2 BN Phase Detector Charge Pump VCO HSCL Outputįigure 2.
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package Offset Noise Power Hz -103 dBc 1 kHz -1 18 dBc 10 kHz -122 dBc 100 kHz -130 dBc 1 MHz -138 dBc 10 MHz -149 dBcOperating Range V ±5%Industrial Temperature Range to +85☌These are Pb-Free Devices Uses 25 MHz Fundamental Mode Parallel Resonant CrystalExternal Loop Filter is Not RequiredHCSL Differential OutputTypical TIE RMS jitter of 2.5 psJitter or Low Phase Noise: This device is housed 4.4 mm narrow body TSSOP 16 pin package. The device takes a 25 MHz fundamental mode parallel resonant crystal and generates differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies.
The is a high precision, low phase noise clock generator that supports PCI-Express and Ethernet requirements.